/*
 * JZ4775 definitions
 *
 * Copyright (c) 2013 Imagination Technologies
 * Author: Paul Burton <paul.burton@imgtec.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __JZ4775_H__
#define __JZ4775_H__

/* AHB0 BUS Devices */
#define	DDRC_BASE				0xb3010000

/* AHB2 BUS Devices */
#define MSC0_BASE				0xb3450000
#define MSC1_BASE				0xb3460000
#define MSC2_BASE				0xb3470000
#define ETHC_BASE				0xb34b0000

/* APB BUS Devices */
#define	CPM_BASE				0xb0000000
#define	TCU_BASE				0xb0002000
#define	GPIO_BASE				0xb0010000
#define	UART0_BASE				0xb0030000
#define	UART1_BASE				0xb0031000
#define	UART2_BASE				0xb0032000
#define	UART3_BASE				0xb0033000
#define	WDT_BASE				0xb0002000

/*************************************************************************
 * CPM (Clock reset and Power control Management)
 *************************************************************************/
#define CPM_CPCCR				0x00 /* Clock control register		*/
#define CPM_CPCSR				0xd4 /* Clock Status register		*/
#define CPM_CPAPCR				0x10 /* APLL control Register		*/
#define CPM_CPMPCR				0x14 /* MPLL control Register		*/
#define CPM_DDRCDR				0x2c /* DDR clock divider register	*/
#define CPM_MSC0CDR				0x68 /* MSC0 clock divider register	*/
#define CPM_MSC1CDR				0xa4 /* MSC1 clock divider register	*/
#define CPM_MSC2CDR				0xa8 /* MSC2 clock divider register	*/
#define CPM_DRCG				0xd0
#define CPM_MPHYC				0xe0

#define CPM_LCR					0x04
#define CPM_CLKGR				0x20 /* Clock Gate Register */
#define CPM_OPCR				0x24 /* Oscillator and Power Control Register */

/* DDR clock divider register */
#define CPM_DDRCDR_DCS_BIT		30
#define CPM_DDRCDR_DCS_MASK		(3 << CPM_DDRCDR_DCS_BIT)
#define CPM_DDRCDR_DCS_STOP		(0x0 << CPM_DDRCDR_DCS_BIT)
#define CPM_DDRCDR_DCS_SCLKA	(0x1 << CPM_DDRCDR_DCS_BIT)
#define CPM_DDRCDR_DCS_MPLL		(0x2 << CPM_DDRCDR_DCS_BIT)
#define CPM_DDRCDR_CE			(1 << 29)
#define CPM_DDRCDR_DDR_BUSY		(1 << 28)
#define CPM_DDRCDR_DDR_STOP		(1 << 27)
#define CPM_DDRCDR_DDRDIV_BIT	0
#define CPM_DDRCDR_DDRDIV_MASK	(0xf << CPM_DDRCDR_DDRDIV_BIT)

/* MSC clock divider register */
#define CPM_MSCCDR_MPCS_BIT		30
#define CPM_MSCCDR_MPCS_MASK	(3 << CPM_MSCCDR_MPCS_BIT)
#define CPM_MSCCDR_MPCS_STOP	(0x0 << CPM_MSCCDR_MPCS_BIT)
#define CPM_MSCCDR_MPCS_SCLKA	(0x1 << CPM_MSCCDR_MPCS_BIT)
#define CPM_MSCCDR_MPCS_MPLL	(0x2 << CPM_MSCCDR_MPCS_BIT)
#define CPM_MSCCDR_CE			(1 << 29)
#define CPM_MSCCDR_MSC_BUSY		(1 << 28)
#define CPM_MSCCDR_MSC_STOP		(1 << 27)
#define CPM_MSCCDR_MSC_CLK0_SEL	(1 << 15)
#define CPM_MSCCDR_MSCDIV_BIT	0
#define CPM_MSCCDR_MSCDIV_MASK	(0xff << CPM_MSCCDR_MSCDIV_BIT)

/* Low Power Control Register */
#define CPM_LCR_PD_X2D			(1 << 31)
#define CPM_LCR_PD_VPU			(1 << 30)
#define CPM_LCR_X2DS			(1 << 27)
#define CPM_LCR_VPUS			(1 << 26)
#define CPM_LCR_PST_BIT 		8
#define CPM_LCR_PST_MASK 		(0xfff << CPM_LCR_PST_BIT)
#define CPM_LCR_DUTY_BIT		3
#define CPM_LCR_DUTY_MASK		(0x1f << CPM_LCR_DOZE_DUTY_BIT)
#define CPM_LCR_DOZE_ON			(1 << 2)
#define CPM_LCR_LPM_BIT			0
#define CPM_LCR_LPM_MASK		(0x3 << CPM_LCR_LPM_BIT)
#define CPM_LCR_LPM_IDLE		(0x0 << CPM_LCR_LPM_BIT)
#define CPM_LCR_LPM_SLEEP		(0x1 << CPM_LCR_LPM_BIT)

/* Clock Gate Register */
#define CPM_CLKGR_DDR			(1 << 31)
#define CPM_CLKGR_EPDE			(1 << 27)
#define CPM_CLKGR_EPDC			(1 << 26)
#define CPM_CLKGR_LCD			(1 << 25)
#define CPM_CLKGR_CIM1			(1 << 24)
#define CPM_CLKGR_CIM0			(1 << 23)
#define CPM_CLKGR_UHC			(1 << 22)
#define CPM_CLKGR_GMAC			(1 << 21)
#define CPM_CLKGR_PDMA			(1 << 20)
#define CPM_CLKGR_VPU			(1 << 19)
#define CPM_CLKGR_UART3			(1 << 18)
#define CPM_CLKGR_UART2			(1 << 17)
#define CPM_CLKGR_UART1			(1 << 16)
#define CPM_CLKGR_UART0			(1 << 15)
#define CPM_CLKGR_SADC			(1 << 14)
#define CPM_CLKGR_PCM			(1 << 13)
#define CPM_CLKGR_MSC2			(1 << 12)
#define CPM_CLKGR_MSC1			(1 << 11)
#define CPM_CLKGR_AHB_MON		(1 << 10)
#define CPM_CLKGR_X2D			(1 << 9)
#define CPM_CLKGR_AIC			(1 << 8)
#define CPM_CLKGR_I2C2			(1 << 7)
#define CPM_CLKGR_I2C1			(1 << 6)
#define CPM_CLKGR_I2C0			(1 << 5)
#define CPM_CLKGR_SSI0			(1 << 4)
#define CPM_CLKGR_MSC0			(1 << 3)
#define CPM_CLKGR_OTG			(1 << 2)
#define CPM_CLKGR_BCH			(1 << 1)
#define CPM_CLKGR_NEMC			(1 << 0)

/* Oscillator and Power Control Register */
#define CPM_OPCR_IDLE_DIS		(1 << 31)
#define CPM_OPCR_MASK_VPU		(1 << 29)
#define CPM_OPCR_L2C_PDEN		(1 << 25)
#define CPM_OPCR_O1ST_BIT		8
#define CPM_OPCR_O1ST_MASK		(0xff << CPM_OPCR_O1ST_BIT)
#define CPM_OPCR_SPENDN0		(1 << 7)
#define CPM_OPCR_SPENDN1		(1 << 6)
#define CPM_OPCR_CPU_MODE		(1 << 5)
#define CPM_OPCR_O1SE			(1 << 4) /* */
#define CPM_OPCR_PD				(1 << 3)
#define CPM_OPCR_ERCS			(1 << 2) /* 0: select EXCLK/512 clock, 1: RTCLK clock */
#define CPM_OPCR_BUS_MODE		(1 << 1)
#define CPM_OPCR_OSE			(1 << 0) /* */

//n = 0,1,2,3,4,5,6
#define GPIO_PXPIN(n)			(0x00 + (n) * 0x100) /* PIN Level Register */
#define GPIO_PXINT(n)			(0x10 + (n) * 0x100) /* Port Interrupt Register */
#define GPIO_PXINTS(n)			(0x14 + (n) * 0x100) /* Port Interrupt Set Register */
#define GPIO_PXINTC(n)			(0x18 + (n) * 0x100) /* Port Interrupt Clear Register */
#define GPIO_PXMASK(n)			(0x20 + (n) * 0x100) /* Port Interrupt Mask Register */
#define GPIO_PXMASKS(n)			(0x24 + (n) * 0x100) /* Port Interrupt Mask Set Reg */
#define GPIO_PXMASKC(n)			(0x28 + (n) * 0x100) /* Port Interrupt Mask Clear Reg */
#define GPIO_PXPAT1(n)			(0x30 + (n) * 0x100) /* Port Pattern 1 Register */
#define GPIO_PXPAT1S(n)			(0x34 + (n) * 0x100) /* Port Pattern 1 Set Reg. */
#define GPIO_PXPAT1C(n)			(0x38 + (n) * 0x100) /* Port Pattern 1 Clear Reg. */
#define GPIO_PXPAT0(n)			(0x40 + (n) * 0x100) /* Port Pattern 0 Register */
#define GPIO_PXPAT0S(n)			(0x44 + (n) * 0x100) /* Port Pattern 0 Set Register */
#define GPIO_PXPAT0C(n)			(0x48 + (n) * 0x100) /* Port Pattern 0 Clear Register */
#define GPIO_PXFLG(n)			(0x50 + (n) * 0x100) /* Port Flag Register */
#define GPIO_PXFLGC(n)			(0x58 + (n) * 0x100) /* Port Flag clear Register */
#define GPIO_PXPEN(n)			(0x70 + (n) * 0x100) /* Port Pull Disable Register */
#define GPIO_PXPENS(n)			(0x74 + (n) * 0x100) /* Port Pull Disable Set Register */
#define GPIO_PXPENC(n)			(0x78 + (n) * 0x100) /* Port Pull Disable Clear Register */

#define GPIO_PA(n)				(0*32 + n)
#define GPIO_PB(n)				(1*32 + n)
#define GPIO_PC(n)				(2*32 + n)
#define GPIO_PD(n)				(3*32 + n)
#define GPIO_PE(n)				(4*32 + n)
#define GPIO_PF(n)				(5*32 + n)
#define GPIO_PG(n)				(6*32 + n)

#define DDR_PHY_OFFSET			0x1000
#define DDR_APB_OFFSET			0x2000

#define DDRC_STATUS				0x0 /* DDR Status Register */
#define DDRC_CFG				0x4 /* DDR Configure Register */
#define DDRC_CTRL				0x8 /* DDR Control Register */
#define DDRC_REFCNT				0x18 /* DDR  Auto-Refresh Counter */
#define DDRC_MMAP0				0x24 /* DDR Memory Map Config Register */
#define DDRC_MMAP1				0x28 /* DDR Memory Map Config Register */
#define DDRC_DLP				0xbc

#define DDRC_TIMING(n)			(0x60 + 4 * (n - 1)) /* DDR Timing Config Register 1-5 */
#define DDRC_REMAP(n)			(0x9c + 4 * (n - 1)) /* DDR Address Remapping Register 1-5 */

#define DDRC_AUTOSR_EN			0x304

#define DDRC_CLKSTP_CFG			(DDR_APB_OFFSET + 0x68)

#define DDRP_PIR				(DDR_PHY_OFFSET + 0x4) /* PHY Initialization Register */
#define DDRP_PGCR				(DDR_PHY_OFFSET + 0x8) /* PHY General Configuration Register*/
#define DDRP_PGSR				(DDR_PHY_OFFSET + 0xc) /* PHY General Status Register*/

#define DDRP_DLLGCR				(DDR_PHY_OFFSET + 0x10) /* DLL General Control Register*/
#define DDRP_ACDLLCR			(DDR_PHY_OFFSET + 0x14) /* AC DLL Control Register*/

#define DDRP_PTR0				(DDR_PHY_OFFSET + 0x18) /* PHY Timing Register 0 */
#define DDRP_PTR1				(DDR_PHY_OFFSET + 0x1c) /* PHY Timing Register 1 */
#define DDRP_PTR2				(DDR_PHY_OFFSET + 0x20) /* PHY Timing Register 2 */

#define DDRP_DSGCR				(DDR_PHY_OFFSET + 0x2c) /* DDR System General Configuration Register */
#define DDRP_DCR				(DDR_PHY_OFFSET + 0x30) /* DRAM Configuration Register*/

#define DDRP_DTPR0				(DDR_PHY_OFFSET + 0x34) /* DRAM Timing Parameters Register 0 */
#define DDRP_DTPR1				(DDR_PHY_OFFSET + 0x38) /* DRAM Timing Parameters Register 1 */
#define DDRP_DTPR2				(DDR_PHY_OFFSET + 0x3c) /* DRAM Timing Parameters Register 2 */
#define DDRP_MR0				(DDR_PHY_OFFSET + 0x40) /* Mode Register 0 */
#define DDRP_MR1				(DDR_PHY_OFFSET + 0x44) /* Mode Register 1 */
#define DDRP_MR2				(DDR_PHY_OFFSET + 0x48) /* Mode Register 2 */

#define DDRP_DTAR				(DDR_PHY_OFFSET + 0x54) /* Data Training Address Register */

#define DDRP_ZQXCR0(n)			(DDR_PHY_OFFSET + 0x180 + n * 0x10) /* ZQ impedance Control Register 0 */
#define DDRP_ZQXCR1(n)			(DDR_PHY_OFFSET + 0x184 + n * 0x10) /* ZQ impedance Control Register 1 */
#define DDRP_ZQXSR0(n)			(DDR_PHY_OFFSET + 0x188 + n * 0x10) /* ZQ impedance Status Register 0 */

#define DDRP_DXGCR(n)			(DDR_PHY_OFFSET + 0x1c0 + n * 0x40) /* DATX8 n General Configuration Register */

/* DDRC Status Register */
#define DDRC_STATUS_ENDIAN		(1 << 7) /* 0 Little data endian
					    1 Big data endian */
#define DDRC_STATUS_MISS		(1 << 6) /* 0 No operation miss DDRC memory mapping
					    1 At least one operation miss DDRC memory mapping */
#define DDRC_STATUS_DPDN		(1 << 5) /* 0 DDR memory is NOT in deep-power-down state
					    1 DDR memory is in deep-power-down state */
#define DDRC_STATUS_PDN			(1 << 4) /* 0 DDR memory is NOT in power-down state
					    1 DDR memory is in power-down state */
#define DDRC_STATUS_AREF		(1 << 3) /* 0 DDR memory is NOT in auto-refresh state
					    1 DDR memory is in auto-refresh state */
#define DDRC_STATUS_SREF		(1 << 2) /* 0 DDR memory is NOT in self-refresh state
					    1 DDR memory is in self-refresh state */
#define DDRC_STATUS_CKE1		(1 << 1) /* 0 CKE1 Pin is low
					    1 CKE1 Pin is high */
#define DDRC_STATUS_CKE0		(1 << 0) /* 0 CKE0 Pin is low
					    1 CKE0 Pin is high */

/* DDRC Configure Register */
#define DDRC_CFG_ROW1_BIT		27 /* Row Address width. */
#define DDRC_CFG_ROW1_MASK		(0x7 << DDRC_CFG_ROW1_BIT)
#define DDRC_CFG_COL1_BIT		24 /* Row Address width. */
#define DDRC_CFG_COL1_MASK		(0x7 << DDRC_CFG_COL1_BIT)
#define DDRC_CFG_BA1			(1 << 23)
#define DDRC_CFG_IMBA			(1 << 22)
#define DDRC_CFG_BL_8			(1 << 21)

#define DDRC_CFG_TYPE_BIT		17
#define DDRC_CFG_TYPE_MASK		(0x7 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_DDR1		(2 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_MDDR		(3 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_DDR2		(4 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_LPDDR2	(5 << DDRC_CFG_TYPE_BIT)
#define DDRC_CFG_TYPE_DDR3		(6 << DDRC_CFG_TYPE_BIT)

#define DDRC_CFG_ODT_EN			(1 << 16)  /* ODT EN */

#define DDRC_CFG_MPRT			(1 << 15)  /* mem protect */

#define DDRC_CFG_ROW_BIT		11 /* Row Address width. */
#define DDRC_CFG_ROW_MASK		(0x7 << DDRC_CFG_ROW_BIT)
#define DDRC_CFG_ROW_12			(0 << DDRC_CFG_ROW_BIT) /* 12-bit row address is used */
#define DDRC_CFG_ROW_13			(1 << DDRC_CFG_ROW_BIT) /* 13-bit row address is used */
#define DDRC_CFG_ROW_14			(2 << DDRC_CFG_ROW_BIT) /* 14-bit row address is used */

#define DDRC_CFG_COL_BIT		8 /* Column Address width.
						Specify the Column address width of external DDR. */
#define DDRC_CFG_COL_MASK		(0x7 << DDRC_CFG_COL_BIT)
#define DDRC_CFG_COL_8			(0 << DDRC_CFG_COL_BIT) /* 8-bit Column address is used */
#define DDRC_CFG_COL_9			(1 << DDRC_CFG_COL_BIT) /* 9-bit Column address is used */
#define DDRC_CFG_COL_10			(2 << DDRC_CFG_COL_BIT) /* 10-bit Column address is used */
#define DDRC_CFG_COL_11			(3 << DDRC_CFG_COL_BIT) /* 11-bit Column address is used */

#define DDRC_CFG_CS1EN			(1 << 7) /* 0 DDR Pin CS1 un-used
					    1 There're DDR memory connected to CS1 */
#define DDRC_CFG_CS0EN			(1 << 6) /* 0 DDR Pin CS0 un-used
					    1 There're DDR memory connected to CS0 */

#define DDRC_CFG_BA				(1 << 1) /* 0 4 bank device, Pin ba[1:0] valid, ba[2] un-used
					    1 8 bank device, Pin ba[2:0] valid*/
#define DDRC_CFG_DW				(1 << 0) /*0 External memory data width is 16-bit
						1 External memory data width is 32-bit */

/* DDRC Control Register */
#define DDRC_CTRL_DFI_RST		(1 << 23)
#define DDRC_CTRL_DLL_RST		(1 << 22)
#define DDRC_CTRL_CTL_RST		(1 << 21)
#define DDRC_CTRL_CFG_RST		(1 << 20)
#define DDRC_CTRL_ACTPD			(1 << 15) /* 0 Precharge all banks before entering power-down
					     1 Do not precharge banks before entering power-down */
#define DDRC_CTRL_PDT_BIT		12 /* Power-Down Timer */
#define DDRC_CTRL_PDT_MASK		(0x7 << DDRC_CTRL_PDT_BIT)
#define DDRC_CTRL_PDT_DIS		(0 << DDRC_CTRL_PDT_BIT) /* power-down disabled */
#define DDRC_CTRL_PDT_8			(1 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 8 tCK idle */
#define DDRC_CTRL_PDT_16		(2 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 16 tCK idle */
#define DDRC_CTRL_PDT_32		(3 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 32 tCK idle */
#define DDRC_CTRL_PDT_64		(4 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 64 tCK idle */
#define DDRC_CTRL_PDT_128		(5 << DDRC_CTRL_PDT_BIT) /* Enter power-down after 128 tCK idle */

#define DDRC_CTRL_DPD			(1 << 6) /* 1 Drive external MDDR device entering Deep-Power-Down mode */

#define DDRC_CTRL_SR			(1 << 5) /* 1 Drive external DDR device entering self-refresh mode
					    0 Drive external DDR device exiting self-refresh mode */
#define DDRC_CTRL_ALH			(1 << 3) /* Advanced Latency Hiding:
					    0 Disable ALH
					    1 Enable ALH */
#define DDRC_CTRL_RDC			(1 << 2) /* 0 dclk clock frequency is lower than 60MHz
					    1 dclk clock frequency is higher than 60MHz */
#define DDRC_CTRL_CKE			(1 << 1) /* 0 Not set CKE Pin High
					    1 Set CKE Pin HIGH */
#define DDRC_CTRL_RESET			(1 << 0) /* 0 End resetting ddrc_controller
					    1 Resetting ddrc_controller */

/* DDRP PHY Initialization Register */
#define DDRP_PIR_INIT			(1 << 0)
#define DDRP_PIR_DLLSRST		(1 << 1)
#define DDRP_PIR_DLLLOCK		(1 << 2)
#define DDRP_PIR_ZCAL			(1 << 3)
#define DDRP_PIR_ITMSRST		(1 << 4)
#define DDRP_PIR_DRAMRST		(1 << 5)
#define DDRP_PIR_DRAMINT		(1 << 6)
#define DDRP_PIR_QSTRN			(1 << 7)
#define DDRP_PIR_EYETRN			(1 << 8)
#define DDRP_PIR_DLLBYP			(1 << 17)
#define DDRP_PIR_LOCKBYP		(1 << 29)

/* DDRP PHY General Status Register */
#define DDRP_PGSR_IDONE			(1 << 0)
#define DDRP_PGSR_DLDONE		(1 << 1)
#define DDRP_PGSR_ZCDONE		(1 << 2)
#define DDRP_PGSR_DIDONE		(1 << 3)
#define DDRP_PGSR_DTDONE		(1 << 4)
#define DDRP_PGSR_DTERR			(1 << 5)
#define DDRP_PGSR_DTIERR		(1 << 6)
#define DDRP_PGSR_DFTEERR		(1 << 7)

/* DDRP DRAM Configuration Register */
#define DDRP_DCR_TYPE_BIT		0
#define DDRP_DCR_TYPE_MASK		(0x7 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_MDDR		(0 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_DDR		(1 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_DDR2		(2 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_DDR3		(3 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_TYPE_LPDDR2	(4 << DDRP_DCR_TYPE_BIT)
#define DDRP_DCR_DDR8BNK_BIT	3
#define DDRP_DCR_DDR8BNK_MASK	(1 << DDRP_DCR_DDR8BNK_BIT)
#define DDRP_DCR_DDR8BNK		(1 << DDRP_DCR_DDR8BNK_BIT)
#define DDRP_DCR_DDR8BNK_DIS	(0 << DDRP_DCR_DDR8BNK_BIT)

#define DDRP_ZQXCR_ZDEN_BIT		28
#define DDRP_ZQXCR_ZDEN			(1 << DDRP_ZQXCR_ZDEN_BIT)

#ifndef __ASSEMBLY__

#include <asm/io.h>

static inline int gpio_get_value(unsigned gpio)
{
	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;
	unsigned port = gpio / 32;
	unsigned pin = gpio % 32;

	return !!(readl(gpio_regs + GPIO_PXPIN(port)) & (1 << pin));
}

static inline void gpio_port_set(int port, int pin, int value)
{
	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;

	if (value)
		writel(1 << pin, gpio_regs + GPIO_PXPAT0S(port));
	else
		writel(1 << pin, gpio_regs + GPIO_PXPAT0C(port));
}

static inline void gpio_port_direction_input(int port, int pin)
{
	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;

	writel(1 << pin, gpio_regs + GPIO_PXINTC(port));
	writel(1 << pin, gpio_regs + GPIO_PXMASKS(port));
	writel(1 << pin, gpio_regs + GPIO_PXPAT1S(port));
}

static inline void gpio_port_direction_output(int port, int pin, int value)
{
	void __iomem *gpio_regs = (void __iomem *)GPIO_BASE;

	writel(1 << pin, gpio_regs + GPIO_PXINTC(port));
	writel(1 << pin, gpio_regs + GPIO_PXMASKS(port));
	writel(1 << pin, gpio_regs + GPIO_PXPAT1C(port));

	gpio_port_set(port, pin, value);
}

static inline void gpio_direction_input(int gpio)
{
	int port = gpio / 32;
	int pin = gpio % 32;

	gpio_port_direction_input(port, pin);
}

static inline void gpio_direction_output(int gpio, int value)
{
	int port = gpio / 32;
	int pin = gpio % 32;

	gpio_port_direction_output(port, pin, value);
}

#endif /* __ASSEMBLY__ */

#endif /* __JZ4775_H__ */
